Every layout consists of several layers that can be used independently
or treated as a group.
Layer groups can be used to logically separate (and color-code)
different traces (e.g. power and signal); however, all
layers within a group reside on the same physical
copper layer of a board, so using different layers within the same
group won't provide electrical separation where they touch or overlap.
For details, see layerGroups
, Resources.
Each layer is drawn in a color defined in the resource file
and identified by a name that you can change (for details
see layerColor
, Resources.)
Layers are really just containers for line, arc, polygon, and text objects. The
component and solder layers contain SMD elements as well, but the
file structure doesn't reflect that fact directly.
Each layer group
represents a physical layer on the printed circuit board. If you want to make
a four layer board, you'll need to have at least four layer groups.
Connections between layer groups are established only through element pins and vias.
The relationship between a specific layer and the board itself is configurable from
the Edit layer groups
option in the Settings menu.
The layer groups corresponding to the physical layers: component-side
and solder-side are always defined and you must map at least one
logical layer to each, even if you plan to make a single-sided board.
You are not obligated to put tracks on either of them.
Surface mount elements always reside on either the component-side or the
solder-side layer group. When you paste an element from the buffer,
it will go onto whichever side of the board you are viewing.
You can swap which side of the board you are viewing by pressing
the Tab key, or by selecting view solder side
from the
Screen menu.
The layer groups just have a name or number associated with them - where
they are sandwiched in the board is left for you to tell the
manufacturer.
The silkscreen layer is special because there are actually two silkscreen layers, one for the top (component) and one for the bottom (solder) side of the board. Which silk layer you draw on is determined by the side of the board that you are viewing. If you are viewing the component side, then drawing on the silk layer draws to the component-side silk layer.
The netlist layer is another special layer. It shows rat's-nest lines
(i.e. guides that show how the netlist expects the element to interconnect).
If you make this the active layer, you can use the Line tool to add
entries into the netlist, or to delete connections from the netlist
window. Except for these two purposes, you should not
make the netlist layer the active layer. Usually there is no need to
do this because a separate schematic package should be used to create the
netlist. Pcb
can automatically draw all of the rats from
the netlist. In some cases you may want to make a small change without
going to the trouble of modifying the schematic, which is why this
facility is provided.