package cuda

/*
 THIS FILE IS AUTO-GENERATED BY CUDA2GO.
 EDITING IS FUTILE.
*/

import (
	"github.com/mumax/3/cuda/cu"
	"github.com/mumax/3/timer"
	"sync"
	"unsafe"
)

// CUDA handle for shiftedgecarryY kernel
var shiftedgecarryY_code cu.Function

// Stores the arguments for shiftedgecarryY kernel invocation
type shiftedgecarryY_args_t struct {
	arg_dst         unsafe.Pointer
	arg_src         unsafe.Pointer
	arg_othercomp   unsafe.Pointer
	arg_anothercomp unsafe.Pointer
	arg_Nx          int
	arg_Ny          int
	arg_Nz          int
	arg_shy         int
	arg_clampD      float32
	arg_clampU      float32
	argptr          [10]unsafe.Pointer
	sync.Mutex
}

// Stores the arguments for shiftedgecarryY kernel invocation
var shiftedgecarryY_args shiftedgecarryY_args_t

func init() {
	// CUDA driver kernel call wants pointers to arguments, set them up once.
	shiftedgecarryY_args.argptr[0] = unsafe.Pointer(&shiftedgecarryY_args.arg_dst)
	shiftedgecarryY_args.argptr[1] = unsafe.Pointer(&shiftedgecarryY_args.arg_src)
	shiftedgecarryY_args.argptr[2] = unsafe.Pointer(&shiftedgecarryY_args.arg_othercomp)
	shiftedgecarryY_args.argptr[3] = unsafe.Pointer(&shiftedgecarryY_args.arg_anothercomp)
	shiftedgecarryY_args.argptr[4] = unsafe.Pointer(&shiftedgecarryY_args.arg_Nx)
	shiftedgecarryY_args.argptr[5] = unsafe.Pointer(&shiftedgecarryY_args.arg_Ny)
	shiftedgecarryY_args.argptr[6] = unsafe.Pointer(&shiftedgecarryY_args.arg_Nz)
	shiftedgecarryY_args.argptr[7] = unsafe.Pointer(&shiftedgecarryY_args.arg_shy)
	shiftedgecarryY_args.argptr[8] = unsafe.Pointer(&shiftedgecarryY_args.arg_clampD)
	shiftedgecarryY_args.argptr[9] = unsafe.Pointer(&shiftedgecarryY_args.arg_clampU)
}

// Wrapper for shiftedgecarryY CUDA kernel, asynchronous.
func k_shiftedgecarryY_async(dst unsafe.Pointer, src unsafe.Pointer, othercomp unsafe.Pointer, anothercomp unsafe.Pointer, Nx int, Ny int, Nz int, shy int, clampD float32, clampU float32, cfg *config) {
	if Synchronous { // debug
		Sync()
		timer.Start("shiftedgecarryY")
	}

	shiftedgecarryY_args.Lock()
	defer shiftedgecarryY_args.Unlock()

	if shiftedgecarryY_code == 0 {
		shiftedgecarryY_code = fatbinLoad(shiftedgecarryY_map, "shiftedgecarryY")
	}

	shiftedgecarryY_args.arg_dst = dst
	shiftedgecarryY_args.arg_src = src
	shiftedgecarryY_args.arg_othercomp = othercomp
	shiftedgecarryY_args.arg_anothercomp = anothercomp
	shiftedgecarryY_args.arg_Nx = Nx
	shiftedgecarryY_args.arg_Ny = Ny
	shiftedgecarryY_args.arg_Nz = Nz
	shiftedgecarryY_args.arg_shy = shy
	shiftedgecarryY_args.arg_clampD = clampD
	shiftedgecarryY_args.arg_clampU = clampU

	args := shiftedgecarryY_args.argptr[:]
	cu.LaunchKernel(shiftedgecarryY_code, cfg.Grid.X, cfg.Grid.Y, cfg.Grid.Z, cfg.Block.X, cfg.Block.Y, cfg.Block.Z, 0, stream0, args)

	if Synchronous { // debug
		Sync()
		timer.Stop("shiftedgecarryY")
	}
}

// maps compute capability on PTX code for shiftedgecarryY kernel.
var shiftedgecarryY_map = map[int]string{0: "",
	50: shiftedgecarryY_ptx_50,
	52: shiftedgecarryY_ptx_52,
	53: shiftedgecarryY_ptx_53,
	60: shiftedgecarryY_ptx_60,
	61: shiftedgecarryY_ptx_61,
	62: shiftedgecarryY_ptx_62,
	70: shiftedgecarryY_ptx_70,
	72: shiftedgecarryY_ptx_72,
	75: shiftedgecarryY_ptx_75,
	80: shiftedgecarryY_ptx_80,
	86: shiftedgecarryY_ptx_86,
	87: shiftedgecarryY_ptx_87,
	89: shiftedgecarryY_ptx_89,
	90: shiftedgecarryY_ptx_90}

// shiftedgecarryY PTX code for various compute capabilities.
const (
	shiftedgecarryY_ptx_50 = `
.version 8.5
.target sm_50
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_52 = `
.version 8.5
.target sm_52
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_53 = `
.version 8.5
.target sm_53
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_60 = `
.version 8.5
.target sm_60
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_61 = `
.version 8.5
.target sm_61
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_62 = `
.version 8.5
.target sm_62
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_70 = `
.version 8.5
.target sm_70
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_72 = `
.version 8.5
.target sm_72
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_75 = `
.version 8.5
.target sm_75
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_80 = `
.version 8.5
.target sm_80
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_86 = `
.version 8.5
.target sm_86
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_87 = `
.version 8.5
.target sm_87
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_89 = `
.version 8.5
.target sm_89
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
	shiftedgecarryY_ptx_90 = `
.version 8.5
.target sm_90
.address_size 64

	// .globl	shiftedgecarryY

.visible .entry shiftedgecarryY(
	.param .u64 shiftedgecarryY_param_0,
	.param .u64 shiftedgecarryY_param_1,
	.param .u64 shiftedgecarryY_param_2,
	.param .u64 shiftedgecarryY_param_3,
	.param .u32 shiftedgecarryY_param_4,
	.param .u32 shiftedgecarryY_param_5,
	.param .u32 shiftedgecarryY_param_6,
	.param .u32 shiftedgecarryY_param_7,
	.param .f32 shiftedgecarryY_param_8,
	.param .f32 shiftedgecarryY_param_9
)
{
	.reg .pred 	%p<14>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<28>;
	.reg .b64 	%rd<27>;


	ld.param.u64 	%rd6, [shiftedgecarryY_param_0];
	ld.param.u64 	%rd7, [shiftedgecarryY_param_1];
	ld.param.u64 	%rd8, [shiftedgecarryY_param_2];
	ld.param.u64 	%rd9, [shiftedgecarryY_param_3];
	ld.param.u32 	%r6, [shiftedgecarryY_param_4];
	ld.param.u32 	%r7, [shiftedgecarryY_param_5];
	ld.param.u32 	%r9, [shiftedgecarryY_param_6];
	ld.param.u32 	%r8, [shiftedgecarryY_param_7];
	ld.param.f32 	%f7, [shiftedgecarryY_param_8];
	ld.param.f32 	%f8, [shiftedgecarryY_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r11, %r10, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r14, %r13, %r15;
	mov.u32 	%r16, %ntid.z;
	mov.u32 	%r17, %ctaid.z;
	mov.u32 	%r18, %tid.z;
	mad.lo.s32 	%r3, %r17, %r16, %r18;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	setp.ge.s32 	%p4, %r3, %r9;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_11;

	sub.s32 	%r4, %r2, %r8;
	setp.lt.s32 	%p6, %r4, 0;
	@%p6 bra 	$L__BB0_7;

	setp.lt.s32 	%p7, %r4, %r7;
	mul.lo.s32 	%r5, %r3, %r7;
	@%p7 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	add.s32 	%r22, %r4, %r5;
	mad.lo.s32 	%r23, %r22, %r6, %r1;
	mul.wide.s32 	%rd16, %r23, 4;
	add.s64 	%rd17, %rd3, %rd16;
	ld.global.nc.f32 	%f13, [%rd17];
	bra.uni 	$L__BB0_10;

$L__BB0_7:
	mul.lo.s32 	%r24, %r3, %r6;
	mad.lo.s32 	%r25, %r24, %r7, %r1;
	cvt.s64.s32 	%rd5, %r25;
	mul.wide.s32 	%rd18, %r25, 4;
	add.s64 	%rd19, %rd3, %rd18;
	ld.global.nc.f32 	%f13, [%rd19];
	setp.neu.f32 	%p11, %f13, 0f00000000;
	@%p11 bra 	$L__BB0_10;

	shl.b64 	%rd20, %rd5, 2;
	add.s64 	%rd21, %rd2, %rd20;
	ld.global.nc.f32 	%f11, [%rd21];
	setp.neu.f32 	%p12, %f11, 0f00000000;
	@%p12 bra 	$L__BB0_10;

	add.s64 	%rd23, %rd1, %rd20;
	ld.global.nc.f32 	%f12, [%rd23];
	setp.eq.f32 	%p13, %f12, 0f00000000;
	selp.f32 	%f13, %f7, %f13, %p13;
	bra.uni 	$L__BB0_10;

$L__BB0_3:
	add.s32 	%r19, %r7, %r5;
	add.s32 	%r20, %r19, -1;
	mad.lo.s32 	%r21, %r20, %r6, %r1;
	cvt.s64.s32 	%rd4, %r21;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.nc.f32 	%f13, [%rd11];
	setp.neu.f32 	%p8, %f13, 0f00000000;
	@%p8 bra 	$L__BB0_10;

	shl.b64 	%rd12, %rd4, 2;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.nc.f32 	%f9, [%rd13];
	setp.neu.f32 	%p9, %f9, 0f00000000;
	@%p9 bra 	$L__BB0_10;

	add.s64 	%rd15, %rd1, %rd12;
	ld.global.nc.f32 	%f10, [%rd15];
	setp.eq.f32 	%p10, %f10, 0f00000000;
	selp.f32 	%f13, %f8, %f13, %p10;

$L__BB0_10:
	mad.lo.s32 	%r26, %r3, %r7, %r2;
	mad.lo.s32 	%r27, %r26, %r6, %r1;
	cvta.to.global.u64 	%rd24, %rd6;
	mul.wide.s32 	%rd25, %r27, 4;
	add.s64 	%rd26, %rd24, %rd25;
	st.global.f32 	[%rd26], %f13;

$L__BB0_11:
	ret;

}

`
)
